Frequency synthesizing circuits are widely used in the architecture of electronic circuits, particularly in the field of telecommunications.
Usually, the problem involves producing a sinusoidal signal which has a frequency having a value which is equal to n times the value of a reference frequency, said frequency being assumed to be steady, such as generated by a quartz oscillator.
In such a situation, the frequency synthesis is achieved by using a Phase Locked Loop (P.L.L.) circuit and the recent general tendency is now to use fully digital architectures for embodying such circuits.
FIG. 1 illustrates a digital architecture of a known frequency synthesizer generating, at an output 6, a high frequency having a value FDCO from a reference frequency FREF which is ideally produced and inserted into an input 12 by a quartz based oscillator.
The synthesizer circuit uses a synchronous clock Fs available in the circuit, and which is generated by a latch having D and CK inputs respectively receiving the reference signal Fref and the output signal FDCO.
A digital word used as a reference is introduced in an input 1 of a digital processing line comprising, in series, a phase accumulator 2, an adder 3 generating at its output an error signal ΦE, a loop filter 4 followed by a normalized oscillator 5 which generates on an output 6 the high frequency signal FDCO.
The adaptive control of the values of the frequency as well as the phase of this signal FDCO is achieved by using two control loops which respectively process the integer and the fractional parts of the desired ratio n of the output frequency FDCO to the reference frequency FREF.
The processing of the integer part is achieved by using a first control loop based on an accumulator 7 and its under-sampling latch 8 clocked by internal clock Fs which allows the counting of the number of rising edges of FDCO between two consecutive rising edges of the reference frequency signal FREF.
The processing of the fractional part of ratio n is achieved by using a second control loop comprising a fractional phase error circuit 10, conventionally designated as a Time to Digital Converter (TDC). This TDC circuit comprises two inputs which respectively receive the reference clock FREF and the synthesized clock FDCO, and which further generates at its output a digital word being representative of the phase error between the edges of the reference signal and the edges of the oscillator 5. The output signal of this fractional phase error circuit is transmitted to adder 3 in order to contribute to the error signal ΦE.
Such is one conventional use of a Time to Digital Converter (T.D.C.) circuit.
FIG. 3 illustrates a well-known embodiment of a TDC circuit, comprising a chain of delays—typically based on inverters 31-1 to 31-L (L being an integer representative of the number of inverting elements within the chain), each delay having an output being connected to an input of a corresponding latch 32-1 to 32-L. The delay chain is adapted so as to extend over a whole period of the high frequency signal FDCO and every latch 32-1 to 32-L receives at its clock input the reference signal FREF.
The outputs of latches 32-1 to 32-L are concatenated in order to constitute one vector which is coded in accordance with a so-called “thermometer” code, which shows transitions between states “1” and states “0”. This code is analyzed by an edge generating circuit which computes the values of the delays between rising edges (Δtr) and falling edges (Δtf), respectively on circuits 37 and 38, then transmitted to a normalized gain circuit 39 used for generating the value 1/TDCO needed for computing the phase error:
  ɛ  =            1      -                        Δ          ⁢                                          ⁢                      t            R                                    T          DCO                      =          1      -                        Δ          ⁢                                          ⁢                      t            R                                    2          ❘                                    Δ              ⁢                                                          ⁢                              t                R                                      -                          Δ              ⁢                                                          ⁢                              t                F                                                        and, applying the conventions shown in the chronogram of FIG. 5, the mean value of the period TDCO can be computed as follows:
            T      _        DCO    =                    1                  N          AVG                    ⁢                        ∑                      k            =            1                                N            AVG                          ⁢                  2          ⁢                                                                Δ                ⁢                                                                  ⁢                                  t                  R                                            -                              Δ                ⁢                                                                  ⁢                                  t                  F                                                                                      ≈                  T        DCO                    t        inv            
The architecture of the frequency synthesizer which was briefly recalled above illustrates the situation of a fully digital implementation, with a PLL adaptive control loop mainly based on a TDC type circuit for achieving the fractional phase error processing 10.
Such a fully digital implementation presents a drawback resulting from the presence of limit cycles within the noise spectrum, as illustrated in FIG. 2.
Limit cycles result from the limitation of the resolution of oscillator 5, which limitation is derived from the quantification step used in the digital frequency synthesis. Because of this quantification step which determines the accuracy of the oscillator, the latter can only generate two neighboring frequencies having two respective values that are one quantification step part, but the same oscillator can certainly not produce any intermediate frequency with a value between those two respective values.
When the loop control becomes working, one can thus notice the appearance of jitter, that is to say the successive generation of two neighboring frequencies being one quantification step apart, and such jitter causes the appearance of parasitic lines as shown in FIG. 2, thus resulting in a non negligible quantification noise.
Such parasitic lines are particularly visible when the value of the output frequency FDCO is equal to n times (with n being an integer) the value of the frequency FREF. In such a situation, one notices a maximum effect of the limit cycles, thus resulting in a non satisfactory quantification noise.
In order to reduce this quantification noise—or more precisely to mitigate its effects—some techniques are available in the art for canceling—or at least significantly reducing—the level of these parasitic lines. One gets then closer to the situation of a white noise. Such techniques for inserting random noise are conventionally designated as dithering techniques.
Generally speaking, known dithering techniques are difficult to embody and results in additional electronic circuits significantly jeopardizing the simplicity of the digital architecture.
Examples of techniques known in the art can be found in the following references:
Document “All-Digital Phase-Domain TX Frequency Synthesizer for Bluetooth Radios in 0.13 pm CMOS” by Staszewski et al, IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE, 2004, Session 15, 272-273, describes a first known realization of a TDC circuit.
U.S. patent application Ser. No. 306,655 (U.S. Patent Application Publication No. 20030141936), filed on Nov. 27, 2002 by Staszewski et al., describes the architecture of a fully digital frequency synthesizer which is based on a digitally controlled oscillator (DCO), which is adjusted by means of a digital control word (OTW).
The patent application filed on Oct. 6, 2003 (U.S. Patent Application Publication No. 20040066240), by Staszewski et al., also describes a frequency synthesizer based on a digitally controlled oscillator.
All those known solutions involve the addition of a random shift at the level of the rising edges of the reference signal FREF, so as to insert a random noise. On the other hand, the implementations show to be complex and particularly require significant changes at the level of every element composing the synthesizing circuit.